FIG. 1 shows the general outline of conventional semiconductor device test equipment together with the internal functional configuration of a pattern generator 10 in particular. The pattern generator 10 is provided with a switch 12, an address counter 14, a pattern-generation memory 16 and a control part 18. In the pattern-generation memory 16 there are provided a test pattern storage part 16A, a control pattern storage part 16B, an operand storage part 16C and a command storage part 16D; a test pattern 24A, a control pattern 24B, an operand 22 and an op code (a Japanese abridged equivalent of operation code) 20 are stored in these storage parts 16A, 16B, 16C and 16D, respectively. The operation code 20 is a sequence control instruction (a Japanese transliteration of “instruction”) such as a branch instruction, and the operand 22 is auxiliary data (such as a jump-to address) necessary for execution of a sequence following the operation code 20. The test pattern 24A contains a test pattern signal which is prepared to make a check to see if a device under test DUT is failing, and an expected value pattern signal which is expected as a normal device response to the input of the test pattern signal.
A description will be given of operations of respective parts for generating the test pattern 24A and the control pattern 24B in the conventional pattern generator 10. To begin with, a start address 26 is preset in the address counter 14 via the switch 12 from the outside. The pattern-generation memory 16 is accessed by the start address 26 to read out the command 20, the operand 22, the test pattern 24A and the control pattern 24B stored in the pattern-generation memory 16. The read-out test pattern 24A is converted by a waveform shaper 27 into a test pattern signal having a real waveform, which is applied via a driver DR to the device under test DUT. The expected value pattern contained in the test pattern 24A is fed to a logic comparator 28. The output signal from the device under test DUT in response to the test pattern signal applied thereto is compared by a comparator CP with a high-level and a low-level voltage, and the comparator output is provided to the logic comparator 28.
The control pattern 24B is supplied to a timing memory 30 and a test cycle memory 34. The timing memory 30 follows a timing pattern in he control pattern 24B to output timing data which defines rise and fall timing of the test pattern signal to be applied to the device under test DUT and the timing for comparing the response output signal from the device under test DUT with the expected value pattern, that is, what is called strobe timing; the timing data is input to a timing generator 32, and timing clocks of various timing are applied to the waveform shaper 27 and the logic comparator 28. Incidentally, in some cases the strobe timing pulse is applied to the comparator CP and at that timing the compared output is provided from the comparator CP.
The test cycle memory 34 follows test cycle data in the control pattern 24B to output period (time) data indicating the time length Ti of each test cycle and send the period data to a test cycle generator 36, causing the test cycle generator 36 to generate a period signal of the time length Ti of each test cycle. The period signal thus generated is applied to the timing generator 32, which generates, within the duration of the test cycle period signal Ti, various timing clocks corresponding to the above-mentioned timing data input thereto. The period Ti is used as the operation period of the pattern generator 10 and is also provided to the control part 18; the control part 18 effects address control for the generation of the next test pattern or the like.
While in FIG. 1 there is shown the configuration for only one pin of the device under test DUT, a similar configuration is used as well for each pin to perform application of the test pattern signal and comparison between the response output signal and the expected value pattern.
Recently there is a demand for speedups of semiconductor devices. To meet this demand, it is necessary, in testing semiconductor devices, too, to apply a high-speed test pattern signal to the device under test DUT. Accordingly, the tendency at present is toward setting short the period (time) Ti of the test cycle.
In the case where the semiconductor device under test DUT has such a circuit configuration as depicted in FIG. FIG. 2 in which functional blocks F1, F2, F3 and F4 are connected in cascade via flip-flops FF2, FF3 and FF4, respectively, if any one of the functional block is failing, the test pattern signal input via an input terminal IN is provided via the flip-flop FF1 to the functional block directly connected thereto; the output from each functional block is provided to the next functional block. Since the test pattern signal input via the input terminal IN is distorted by the failing functional block before it is provided as the output from the functional block F4 to an output terminal OUT via a flip-flop FF5, the response output signal from the output terminal OUT does not agree with the expected value pattern, and consequently the device under test is decided as failing (a failure).
There is a variety of possible causes for the failure of the device under test DUT; for instance, when one of functional blocks does not meet the timing specification set forth in the design of the device, data cannot correctly be transferred from that functional block to the next one—this may sometimes lead to a failure. To locate the functional block in which such a failure has occurred, it is customary to adopt a test scheme referred to as cycle stretch.
With the cycle stretch scheme, a sequence of test pattern signals is applied to a cascade-connected circuit of a functional block whose output was found failing in preliminary testing with a high-speed test pattern signal; in this instance, the period of only one of test cycles of test pattern signals is cycle-stretched to be longer than the test cycle period in ordinary high-speed testing and a check is made to see if the output from the cascade-connected circuit of the failing functional block is still failing, followed by testing while cycle-stretching the test cycles one after another, for example, in the order of first test cycle—second test cycle—third test cycle . . . , and when the output from the cascade-connected circuit of the failing functional block changes from fail to pass (good), it is decided that the functional block of the stage following the first-stage functional block by the number of cycle stretches iterated until then does not satisfy the timing specifications.
Referring now to FIGS. 2 to 7, the general outline of the cycle stretch test scheme will be described in brief. The description will be given of the case where the functional block F2 second from the input terminal IN in the cascade connection of the functional blocks shown in FIG. 2 is incapable of high-speed operation and malfunctions in the high-speed pattern signal test (an ordinary test).
Let it be assumed that in first, second, . . . test cycles, clocks CLK1, CLK2, CLK3, CLK4, . . . of defined periods are applied to all the flip-flops FF1, FF2, . . . , FF5 in the order of period data T1-T2-T3-T2 and that pieces of data processed in the respective functional blocks are sequentially transferred from the functional block F1 to F2, from F2 to F3 and from F3 to F4 for each of the clocks CLK1, CLK2, CLK3, CLK4, . . . .
FIG. 4 shows the input/output state of the respective functional blocks in the case where the test cycles are conducted in the order of the periods T1-T2-T3-T2- . . . , that is, in the case where the blocks were tested using an ordinary high-speed test pattern signal. Letting T1, T2 and T3 represent the periods defined by the period data, respectively, and assuming, for example, that T1<T2<T3, the transfer of data a from the flip-flop FF1 to FF2 takes place in the period of the period data T1, the transfer of data a from the flip-flop FF2 to FF3 takes place in the period of the period data T2, the transfer of data a from the flip-flop FF3 to FF4 takes places in the period of the period data T3, and the transfer of data from the flip-flop FF4 to an output terminal OUT takes place in the period of the period data T2. In the test using these pieces of high-speed period data T1, T2 and T3, assuming that the functional block F2 malfunctions, the processed data a(x) to be transferred to the functional blocks F3 and F4 is already distorted in the functional block F2, and consequently, the processed data a(x) that is output to the output terminal OUT in the fifth test cycle is judged failed FL.
To avoid this, the cycle stretch test scheme is adopted; in the first place, as shown in FIG. 5, only the first test cycle is cycle-stretched to provide period data T4 which defines a cycle period longer than that by any of the pieces of high-speed period data T1, T2 and T3 (T1<T2<T3<T4). In the first test cycle, data a is input to the flip-flop FF1, then the input is processed in the functional block F1, and at the beginning of the second test cycle the output from the functional block F1 is provided to the flip-flop FF2 and transferred therefrom to the functional block F2. Since the functional block F1 is a normal block, the processed data a is normally processed and transferred to the function block F2 of the second stage; however, since the period length of the second test cycle is T2 which is one of pieces of high-speed period data, the functional block F2 cannot normally process the input data within the period of the second test cycle, and at the beginning of the third test cycle bad data a(x) distorted from a normal processed value is input to the flip-flop FF3. Thereafter the bad data a(x) is output to the output terminal OUT via the functional blocks F3 and F4, and hence the data thus provided to the output terminal OUT is judged failed FL in the fifth test cycle.
Next, as depicted in FIG. 6, only the second test cycle is cycle-stretched, by which in the second test cycle the processing period in each functional block is extended to T4. In this case, since the period of the second test cycle is sufficiently long, the functional block F2 processes the input data thereto normally, and at the beginning of the third test cycle the normally processed data a(O) is provided to the flip-clop FF3, from which it is input to the functional block F3. As a result, the normally processed data a(O) is transferred to the functional blocks F3 and F4 one after the other and output to the output terminal OUT, and in the fifth test cycle the test result becomes a pass PA.
As described above, the test cycles are cycle-stretched in a sequentially order starting from the first test cycle, and since the number of times the cycle stretch has been performed until the decision result on the output at the output terminal OUT changes from failed FL to good (pass) PA is 2, it can be decided that the functional block F2 second from the first-stage one F1 does not fulfill the timing specifications.
FIG. 7 shows the case where the cycle stretch is performed in the third test cycle and the processing time in each functional block is set to T4. In this instance, since the malfunctioning functional block F2 is allowed to process data a in the second test cycle for only the period of the period data T2 which is one of the pieces of high-speed period data, the data input as the output from the functional block F2 to the flip-flop F3 at the beginning of the third test cycle become failed data a(x), and this failed data a(x) is output from the functional block F4 to the output terminal OUT, with the result that the decision result in the fifth test cycle becomes failed FL.
It will be easily understood that when the period data T4 is similarly set for the fourth test cycle (cycle-stretched), the output at the output terminal OUT in the fifth test cycle is decided failed FL. Accordingly, as opposed to the above, the cycle stretch may also start from the test cycle immediately preceding the test cycle in which the output decision result was decided as failed and proceed toward the first test cycle on a cycle-by-cycle basis such that, in the above case, the fourth test cycle immediately preceding the fifth one in which the output decision result was decided as failed FL is cycle-stretched first, followed by the third test cycle; in this instance, when the output decision result changes from failed FL to good (pass) after N cycle-stretch iterations, that is, when the functional block F2 Nth from the last in FIG. 2 is failing, the output decision result changes from failed to pass PA after three cycle-stretch iterations, making it possible to decide that the functional block F2 third from the last does not meet the timing specifications. Usually the test pattern to be applied to the device under test DUT is composed of many test cycles and hence is long, and for each test cycle a check is made to see if the device output is failed or not. Accordingly, when the device output is decided as failed, for example, in an M-th test cycle, the test is conducted while stretching the preceding test cycles one after another, that is, in the order of M−1, M−2, . . . , by which the time for deciding the failing functional block can be reduced.
As is evident from the above, by repeating the test while sequentially stretching (a Japanese equivalent of the word) the time for data transfer between the cascade-connected functional blocks F1, F2, F3 and F4, it is possible to detect a functional block which operates normally only when the cycle period is stretched, and the detected information can be used as a material for semiconductor device developments.
To conduct the above-described cycle stretch scheme, in the prior art the period data for cycle stretch, T4 in the above example, is stored in the test cycle memory 34 in the pattern generator 10 in FIG. 1, then the test cycle data in the control pattern 24B of the test pattern stored in the memory 16 at the address corresponding to the first test cycle is rewritten to the cycle stretch period data T4, after which the test is conducted; that is, the test is carried out after cycle-stretching the first test cycle, then the test cycle data rewritten for the first test cycle is restored to the original test cycle data and, at the same time, the test cycle data in the control pattern 24B at the address corresponding to the second test cycle is rewritten to the period data T4, and the test is carried out, and thereafter, similarly in the subsequent test cycles the rewritten test cycle data for the previous test cycle is restored to the original and the test cycle data in the control pattern 24B corresponding to the next test cycle is rewritten to the cycle stretch data therefor, and the test is carried out until the test result changes from failed FL to good PA.
The rewriting of the test cycle data and its restoration to the original test cycle data for each test cycle involve rewriting the pattern program to the original data and translating the pattern program for the rewriting and the restoration to the original data into machine language readable by the test equipment, and since this carried out for each test cycle, much time is taken for the data rewriting and data restoration. Furthermore, the data restoration requires saving of the original data, for example, T2.
Moreover, in the prior art, as data indicating whether to execute cycle stretch or not, period data, which is not used in the high-speed pattern test signal, is written in the pattern-generation memory 16 at the address concerned, but in the case where period data is already written in the test cycle data memory 34 at every address, it is not clear from the contents of the memory 34 as to whether there is period data usable for the cycle stretch concerned, and if any, which data is usable.
Incidentally, since in the test using an ordinary high-speed test pattern signal no check is made as to which data was used as the test cycle data, the control pattern storage part 16B of the pattern-generation memory 16 is read out to check which test cycle data to be used in the high-speed test pattern signal was used; that is, in the above example it is checked that the test cycle data used is T1, T2 and T3, and use is made of the period data T4 not used. Looking for such unused period data consumes much labor and time when the number of test cycles of the high-speed pattern signal is large.
For example, since the period data that can be stored in the test cycle memory 34 is limited to four pieces of data T1, T2, T3 and T4, if the number of piece of period data necessary for test is “4” and the number of pieces of period data that can be stored is “42,” the prior data to be used for cycle stretch, for example, T5, cannot be stored in the test cycle memory 34 and no cycle stretch test can be carried out.
An object of the present invention is to propose a semiconductor device test method and semiconductor device test equipment which permit easy execution of cycle stretch in a required test cycle and sequential stretch of test cycles without causing an appreciable increase in the amount of time for test, and enable cycle stretch to be performed even if no period data for cycle stretch can be stored in the test cycle memory because it is already full.